Getting Started with Morello and Yocto
The ‘Morello’ project was an experimental research architecture developed by ARM that implemented the CHERI instruction extensions. The hardware was based on Neoverse N1 core, which itself was based on the Armv8.2-A architecture specification, but it was constrained to ‘AArch64’ execution only. The memory tagging functionality (which is required to accommodate the capabilities) was managed by a custom memory controller and interconnect: tags were stored in the DDR ECC bit or in DRAM at the top of physical memory address space.
Read More